Manycore IP Framework

Heterogeneous Manycore IP Framework

Cyceera’s vision for the future of computing is one that is cognitive, reconfigurable, highly parallel and heterogeneous. Legacy architectures and their programming models are no match for emerging complex, highly parallel computing and software applications. Cyceera has been developing a range of parallel processing and machine learning technologies, which exploit the features of our patented heterogeneous manycore technology and overcomes many of the limitations of current sequential processing technologies.

Cyceera’s patented parallel programming model provides a wealth of novel features that bring a mix of processor programmability, FPGA style flexibility and all with the performance characteristics of an ASIC or System on Chip (SoC) devices. Our technology enables the creation of powerful parallel processing devices that address the constantly increasing demands of reduced size, reduced power dissipation and greater throughput while offering flexible configurable hardware and targeted performance.

Function Blocks

Modular and scalable spatial – dataflow inspired architecture comprising arrays of addressable fine and coarse grained function blocks connected by a simple Network on Chip (NoC) allowing hardware resources to be shared by different threads. The architecture limits data movement by processing the data where it is generated – stored where possible. Other key features are:

  • Implements various levels of parallelism, including instruction, data, logic, thread, task, storage and IO.
  • Fast hardware self-synchronizing thread mechanism that reduces overheads and is transparent to programmers.
  • Optimizes hardware resource utilization through autonomous asynchronous scheduling and Out Of Order Execution (OoOE).
  • Control hardware is also fragmented and shared by different threads to optimize utilization and reduce silicon real estate. Program code size and hence memory requirements are reduced.