Manycore Parallel Programming
Cyceera’s innovative technology will provide system developers, both software and hardware, with the means to easily analyse and implement highly parallel problem spaces. Similar to Partitioned Global Address Space (PGAS), our programming model provides programmers a shared address space model that simplifies programming while enhancing performance through locality awareness. Our programming model is supported directly by the hardware. However, designers do not need to be fully familiar with the internal operations of the hardware to program the device. The novel self-
The programming model incorporates a dataflow style approach. A problem space is recursively partitioned into multiple threads to exploit the fine degree of parallelism provided by Cyceera’s architecture. The result is analogous to a dynamic directed graph where nodes represent Function Blocks. The threads run on the array of shared resource Function Blocks and independent threads can access the resources of the same Function Block. Operations or tasks within a thread can be coded as codelets that run on processor type Function Block (e.g. VLIW) and or be configuration data that configure Function Blocks to implement tasks in hardware. The addressable Function Blocks allow results in the form of tokens to be routed automatically to other Function Blocks as defined in the directed graph in order to implement the desired algorithm.
As the Function Blocks are self-